With the development of the semiconductor technology, integrated circuits with higher performance and more powerful functions require greater element density. Thus, the sizes of the components need to be scaled further. The utilization of the core technology for 32/22 nanometer process of integrated circuits has been the inevitable trend for the development of integrated circuits, which are also the projects for major international semiconductor companies and institutions to compete to develop. Study on CMOS device gate engineering with “high-k/metal gate” as the core technology is the most representative in 32/22 nanometer technology, and relevant studies on materials, processes and structures are conducted extensively.
For an MOS device having a high k/metal gate structure, the quality of high-k gate dielectric film, especially the oxygen vacancies and defect density of the high-k gate dielectric film, is essential for the continuous improvement of the performance of the whole device. Currently, hafnium (HO-base high-k gate dielectric film has become the most promising candidate for industrial materials, and has been successfully applied to the 45 nm and 32 nm processes of Intel Corporation. However, there exists serious problems caused by oxygen vacancies in the Hf-base high-k gate dielectric film, for example, degradation of the threshold voltage, mobility of channel carriers, and reliability, etc. It also has negative influence on the threshold voltage of a device, for example, Fermi level pinning effect, and flat band voltage roll-off (Vfb roll-off) in a PMOS device, etc. Therefore, it has become a challenge in production of an MOS device, particularly a PMOS device, to alleviate the density of oxygen vacancy defects in the high-k gate dielectric film.
In the current method of manufacturing a high-k gate dielectric/metal gate structured MOS device, the high-k film layer grown by a chemical method (for example, an Atomic Layer Deposition (ALD) or Metal Organic Chemical Vapor Deposition (MOCVD)) generally has more defects and charge traps, and insufficient compactness in the high-k gate dielectric film. In order to increase the compactness of the high-k gate dielectric film and meanwhile alleviate oxygen vacancy and defect traps, a post-deposition-annealing (PDA) process may be conducted at a temperature in the range of about 400-1100° C. However, in this process, oxygen in the annealing atmosphere will enter into the MOS device having a high-k gate dielectric/metal gate structure due to diffusion at a high temperature, and pass through the dielectric layer, and finally arrive at the SiO2/Si interface to react with the silicon substrate and generate SiO2, and thereby the thickness of SiO2 interface layer will be decreased. This will disadvantageously lead to increase of Equivalent Oxide Thickness (EOT) of the whole gate structure, and finally lead to degradation of the overall performance for the MOS device. Furthermore, during the MOS device manufacturing process, annealing is required at a temperature in the range of about 950-1100° C. to activate the dopants in source/drain regions. During this thermal treatment process, oxygen in the high-k gate dielectric film will be diffused into the SiO2/Si interface, and lead to oxygen vacancy defects in the high-k gate dielectric film. Utilization of the high-k gate dielectric and the metal gate electrode in a PMOS device may have some disadvantages. For example, these defects may seriously affect the threshold voltage of the device, in particular the threshold voltage feature of the PMOS device. Therefore, it has become a challenge in production of nanometer CMOS devices to alleviate the increase of the threshold voltage caused by oxygen vacancy.
Therefore, in order to improve the performance of a CMOS device having a high-k gate dielectric/metal gate structure, there is a need for a semiconductor device and a method of manufacturing the same.